Most current-generation dynamic random access memories (DRAMs) utilize CMOS technology. Although the term "CMOS" is an acronym for (C)omplementary (M)etal (O)xide (S)emiconductor, the term CMOS is now more loosely applied to any integrated circuit in which both N-channel and P-channel field-effect transistors are used in a complementary fashion. Although CMOS integrated circuit devices are often referred to as "semiconductor" devices, such devices are fabricated from various materials which are either electrically conductive, electrically nonconductive or electrically semiconductive. Silicon, the most commonly used semiconductor material can be made conductive by doping it (introducing an impurity into the silicon crystal structure) with either an element such as boron which has one less valence electron than silicon, or with an element such as phosphorus or arsenic which have one more valence electron than silicon. In the case of boron doping, electron "holes" become the charge carriers and the doped silicon is referred to as positive or P-type silicon. In the case of phosphorus or arsenic doping, the additional electrons become the charge carriers and the doped silicon is referred to as negative or N-type silicon If a mixture of dopants having opposite conductivity types is used, counter doping will result, and the conductivity type of the most abundant impurity will prevail. Silicon is used either in single-crystal or polycrystalline form. Polycrystalline silicon is referred to hereinafter as "polysilicon" or simply as "poly". Although polysilicon has largely replaced metal for the MOS device gates, the inherently high conductivity of a metal has led many semiconductor manufacturers to create a layer of refractory metal silicide on transistor gates in order to increase device speed.
CMOS processes begin with a lightly-doped P-type or N-type silicon substrate, or lightly-doped epitaxial silicon on a heavily doped substrate. For the sake of simplicity, the prior art CMOS process will be described using P-type silicon as the starting material. If N-type silicon were used, the process steps would be virtually identical, with the exception that in some cases, dopant types would be reversed.
In 1982, Japanese patent number 57-17164 was issued to Masahide Ogawa. This patent teaches the fabrication of a CMOS integrated circuit by processing N-channel and P-channel devices separately. As with conventional CMOS processes, a single polysilicon layer is used to form both N-channel and P-channel gates. However, N-channel devices are formed first, with unetched polysilicon left in the future P-channel regions until N-channel processing is complete. The mask used to subsequently pattern the P-channel devices is also used to blanket and protect the already-formed N-channel devices. This process is herein referred to as the split-polysilicon CMOS process. The split-polysilicon CMOS process, though largely ignored by semiconductor manufacturers in the U.S. and abroad, has been used extensively by Micron Technology, Inc. of Boise, Idaho as a means to reduce the mask sets and, hence, the cost of manufacturing dynamic random access memories.
The memory cells of dynamic random access memories are comprised of two main components: a field-effect transistor and a capacitor. In DRAM cells utilizing a conventional planar capacitor, far more chip surface area is dedicated to the planar capacitor than to the field-effect transistor (FET). Wordlines are generally etched from a polysilicon-1 layer. A doped region of silicon substrate functions as the lower (storage-node) capacitor plate, while a doped polysilicon-2 layer generally functions as the upper capacitor plate (cell plate). Although planar capacitors have generally proven adequate for use in DRAM chips up to the one-megabit level, they are considered to be unusable for more advanced DRAM generations. As component density in memory chips has increased, the shrinkage of cell capacitor size has resulted in a number of problems. Firstly, the alpha-particle component of normal background radiation can generate hole-electron pairs in the silicon substrate, which can be collected by the lower capacitor plate. This phenomena will cause a charge stored within the affected cell capacitor to rapidly dissipate, resulting in a "soft" error. Secondly, the sense-amplifier differential signal is reduced. This aggravates noise sensitivity and makes it more difficult to design column sense-amplifiers having appropriate signal selectivity. Thirdly, as cell capacitor size is decreased, the smaller charge stored within the cell leaks to an unusable level sooner, which necessitates more frequent interruptions for refresh overhead. The difficult goal of a DRAM technologist is therefore to increase or, at least, maintain cell capacitance as cell size shrinks, without resorting to processes that reduce product yield or that markedly increase the number of masking, deposition, etch, implant, sputter, and other steps in the production process.
As a result of the problems associated with the use of planar capacitors for high-density DRAM memories, all manufacturers of 4-megabit DRAMs are utilizing cell designs based on non-planar capacitors. Two basic non-planar capacitor designs are currently in use: the trench capacitor, and the stacked capacitor. Both types of non-planar capacitors typically require a considerably greater number of masking, deposition and etching steps for their manufacture than does a planar capacitor.
In a trench capacitor, charge is stored primarily vertically, as opposed to horizontally in a planar capacitor. Since trench capacitors are fabricated in trenches which are etched in the substrate, some trench capacitor structures can be susceptible to soft errors. In addition, there are several other problems inherent in the trench design. One problem is that of trench-to-trench charge leakage, caused by the parasitic transistor effect between adjacent trenches. Another problem is cell storage node-to-substrate leakage attributable to single crystal defects which are induced by stress associated with the trench structure. Yet Another problem is the difficulty of completely cleaning the trenches during the fabrication process; failure to completely clean a trench will generally result in a defective cell.
The stacked capacitor design, on the other hand, has proven somewhat more reliable and easier to fabricate than the trench design. Consequently, most manufacturers of 4-megabit DRAMs are utilizing stacked capacitor designs. Since both the lower and the upper plates of a typical stacked capacitor are formed from individual conductive layers, the stacked capacitor is generally much less susceptible to soft errors than either the planar or trench capacitors. By placing the wordline and, in some designs, also the bitline beneath the capacitive layers, and having the lower layer make contact with the substrate by means of a buried contact, some manufacturers have created stacked capacitor designs in which vertical portions of the capacitor contribute significantly to the total charge storing capacity. Since a stacked capacitor generally covers not only the entire area of a cell (including the cell's access FET), but adjacent field oxide regions as well, capacitance is considerably enhanced over that available from a planar type cell.
The business of producing CMOS semiconductor devices is a very competitive, high-volume business. Process efficiency and manufacturability, as well as product quality, reliability, and performance are the key factor that determine the economic success of such a venture. Each new generation of CMOS devices generally has an integration level that is four times that of the generation which it replaced. Such a quadrupling of device number per chip is usually accompanied by a decrease in device geometries. As device geometries shrink, each photolithographic step becomes more costly. The increase in cost may be attributed to a number of factors, including:
(a) higher capital costs for precision "state-of-the-art" photolithographic equipment;
(b) an increase in the number of processing steps for each mask level, which slows the fabrication process and requires additional expensive equipment;
(c) the requirement for ultra-clean fabrication facilities which are both expensive to construct and expensive to operate;
(d) greater investment per wafer during fabrication, which increases the cost of scrapping defective devices; and
(e) costs associated with the step required subsequent to the masking step, whether it be an implant or an etch.
Triple polysilicon layer manufacturing processes for contemporary stacked-capacitor dynamic random access memories require some fourteen to eighteen masking steps. In light of the costs associated with masking operations, a manufacturing process which requires a dramatically-reduced number of masking operations would be greatly preferred.